1. Field
Embodiments of the present invention relate to a flash memory device and, more particularly, to a technology for changing a shape of a source line and an arrangement structure of a discharge region.
2. Description of the Related Art
A NAND flash memory serving as a non-volatile semiconductor memory device has integration and memory capacity that meet the requirements of dynamic random access memories (DRAMs), so that the usage and availability of NAND flash memory is rapidly increasing. NAND flash memory is generally configured in a structure where a memory string and memory cells are connected in series and coupled between a bit line and a source line. Many memory strings are then arranged to form a memory cell array.
A conventional ash memory device according to the related art will hereinafter be described with reference to FIGS. 1 and 2.
FIG. 1 is a circuit diagram illustrating a conventional flash memory device, and FIG. 2 is a layout diagram illustrating the conventional flash memory device of FIG. 1.
Referring to FIG. 1, the flash memory device includes a cell array region in which a plurality of memory blocks BLK are disposed.
The memory blocks BLK include a plurality of word lines WL and a plurality of bit lines BL, and the word lines WL and the bit lines BL arranged to cross each other.
Conventionally, a source line (SL) discharge transistor (TR) region is arranged adjacent to the cell array region in a bit line direction as shown in FIGS. 1 and 2.
The SL discharge TR region may include a plurality of gate electrodes and source/drain junction regions. A first source line SL1 extending in a word line direction is disposed between memory blocks BLK and coupled to source selection transistors SST of the memory blocks BLK. The memory blocks BLK of the cell array region are coupled to the source junction region of the SL discharge TR region through a second source line SL2 that is coupled to the first source line SL1.
In this example, the second source line SL2 may be formed in a mesh-shaped pattern in which line patterns are formed to cross each other in a lattice shape as shown in FIG. 2.
An X-decoder region is arranged adjacent to the cell array region in the word line direction. The X-decoder region may include a decoder switch DEC_SW and a pass transistor PASS TR. The decoder switch DEC_SW includes a block word line BLKWL, the block word line BLKWL may be coupled to gate electrodes of the pass transistor PASS TR composed of high-voltage transistors. Since the second source line SL2 formed in the mesh-shaped pattern is formed in the cell array region, it is difficult to implement a structure in which the block word line BLKWL passes through the cell array regions.
Therefore, a decoder switch DEC_SW is required for each pass transistor PASS TR, and it is difficult to share the pass transistors PASS TR among the cell array regions so that the memory device unavoidably increases in size.